(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of forming a strained silicon channel region via formation of adjacent silicon-germanium source/drain regions.
(2) Description of Prior Art
The performance of semiconductor devices, specifically metal oxide semiconductor field effect transistor (MOSFET) devices, has been enhanced via the use of a strained silicon layer used to accommodate the device channel region. The strained silicon layer allows the device channel region to experience increased carrier mobility thus increased device performance. One method of forming a strained silicon layer is to grow the silicon layer on an underlying relaxed layer such as a silicon-germanium layer. The attainment of the relaxed silicon-germanium layer can however present a layer comprised with dislocations wherein the same dislocations can propagate to a subsequently grown overlying strained silicon layer. Therefore the enhanced device performance realized with the underlying relaxed layer can however be compromised by possible device leakage due to the propagated dislocations. A second method of forming a strained silicon layer is the formation of source/drain regions comprised of a semiconductor alloy layer such as a silicon-germanium layer. The silicon region located between semiconductor alloy source/drain regions is now in a strained state allowing the enhanced device performance to be achieved. Methods used to form semiconductor alloy source/drain regions can however add unwanted process complexity resulting in lower device yields as well as increased fabrication costs. An example of a process used to form silicon-germanium source/drain regions is the etching or trenching of semiconductor material followed by refill with silicon-germanium. The above process sequence now however requires the semiconductor trenching or recessing procedure which increases process complexity and cost.
The present invention will describe a method of forming a semiconductor device in which a strained silicon channel region is formed between semiconductor alloy source/drain regions however without the complexity of recessing semiconductor material followed by refilling with the semiconductor alloy material. Prior art such as Murthy et al in U.S. Pat. No. 6,621,131 B2, Fitzgerald in U.S. Pat. No. 6,724,008 B2, Doris et al in U.S. Pat. No. 6,717,216 B1, Yamazaki in U.S. Pat. No. 6,770,546 B2, Puchner et al in U.S. Pat. No. 6,544,854 B1, and Yeo et al in 2004/0173815 A1, have described methods of forming a strained silicon layer to accommodate a device channel region, however none of the above prior art describe the unique process sequence of the present invention in which a strained silicon region is formed between semiconductor alloy source/drain regions, wherein the semiconductor alloy source/drain regions are formed using an optimized process sequence that does not require recessing semiconductor material followed by refilling with the semiconductor alloy material.